1. Field of the Invention
The present invention relates generally to data transfer methodologies, more particularly, to a return path clocking technique.
2. Description of the Related Art
One of the difficulties with conventional bus architectures running at high speed is that as the bus gets longer, propagation time causes an increasing delay for signals transmitted between widely separated devices. For instance, in systems that include a master device and a plurality of slave devices, it is often difficult to get signals from a near slave device and a distant slave device back to a receiving latch in the master device such that signals from both near and far devices meet setup and hold times within one clock cycle at the master latch.
Various techniques have been implemented to match the physical latency requirements to the speed of a bus. Typically, bus specifications define upper bounds on the spacing for components on the bus and the number of loads on the bus, with shorter distances and a reduced number of loads mandated for higher speed buses. PCI-66, at 66 MHz, for example, permits shorter overall trace length and fewer connected components than PCI-33, at 33 MHz. Some mechanism may use a central clock generator that carefully skews clocks for each connected component, so that the clocks compensate for the distance variations. Other mechanisms may use a source-synchronous clock, so that every transmitting device generates its own clock. Most bus architectures usually provide separate signal paths for outbound and return signals.
Using a central clock generator that skews clocks for each connected component typically increases the complexity and cost of the design, either in a custom chip or in a PLL-based addition to a master device. Reducing the overall bus length may be unacceptable if the goal of the bus is to interconnect devices that are widely separated. Similarly, if the design goals of the bus include interconnecting a significant number of devices, reducing the number of loads may not be a viable option. Some systems use point-to-point interconnection, in a ring or star configuration. However, this usually requires an increase in the number of pins required per device. Source-synchronous clocking may reduce potential bus bandwidth (by using a signal for the source clock) and may complicate termination of bus lines. Using separate signal paths for outbound and return signals may require an unacceptable increase in the number of traces as well as pins on the master and slave devices.
Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.